1. Field of the Invention
The present invention relates to a microcomputer development support system, and more specifically to a microcomputer development support system used for development of a microprocessor having a cache memory therein.
2. Description of Related Art
Recent microprocessors are apt to internally contain a cache memory for attaining a high speed memory access. Accordingly, the performance of microprocessors has become high, but, the work for debugging a system constituted of this type of microprocessor internally containing the cache memory, has become difficult. The reason for this is that this type of microprocessor outputs its execution states only when a memory access is "mishit" (e.g., a "miss") in the cache memory, and therefore, it is not possible to monitor the current execution state of the program by tracing the memory access.
In the case of debugging a system having this type of microprocessor, a microcomputer development support system is used. When only the executing process of a program is to be traced by the microcomputer development support system, all memory accesses required by the microprocessor can be outputted to an external of the microprocessor by making the cache memory of the microprocessor inactive (this state is called "cache off "). However, this tracing under the "cache off " state is greatly different in an executing time from a real operation of the microprocessor performed using the cache memory, and therefore, this debugging method is not so effective for a system required to have a real-time operation.
In order to debug a real time operation while using the microcomputer development support system, a break function is used to obtain the real time result. This break function causes the microprocessor to execute a branch instruction at an arbitrary address of a program, and on the other hand, at a branch destination address there is beforehand prepared program for outputting an internal condition of the microprocessor and an intermediate result of the program execution which the user wishes to know, so that the user can observe whether or not an expected processing has been executed.
One typical conventional break function is disclosed in Japanese Patent Application Laid-open Publication No. Hei 03-078038 (JP-A-3-078038) entitled "In-Circuit Emulator".
Now, this typical conventional break function will be described with reference to FIG. 1 which is a block diagram of the "In-Circuit Emulator"shown in JP-A-3-078038 and also with reference to FIG. 2 which is a timing chart illustrating an operation of the "In-Circuit Emulator".
In FIG. 1, a microcomputer development support system is constituted by elements located at a right side of a line 600, and is coupled to a microprocessor 61 having a cache memory therein and coupled to a first data bus 601 and an address bus 603.
More specifically, the microcomputer development support system includes a user memory 62, which is divided into a user space and a front-end monitor which is required to operate the microcomputer development support system (it is necessary for the user of the microcomputer development support system to prepare this memory region for a microcomputer development support system).
The microcomputer development support system also includes a background monitor 65, independently of the user memory 62, and coupled to a second data bus 602, which is also coupled to the user memory 62. A memory space switching circuit 67 is coupled to the address bus 603 and the user memory 62 through another address bus 610. This memory space switching circuit 67 operates to separate the background monitor 65 from the user space under the control of the front-end monitor.
A breakpoint register 64 coupled to the second data bus 602 and configured to be set with a break point by a user. A comparator 66 has a first input coupled to the address bus 603 and a second input coupled to the breakpoint register 64, for generating a coincidence signal or break request signal 607 when a coincidence is detected.
The microcomputer development support system also includes an instruction substituting circuit 63 which is coupled to the microprocessor 61 through the first data bus 60I and to the user memory 62 through the second data bus 602, and which is controlled by the break request signal 607 outputted from the comparator 66. This instruction substituting circuit 63 substitutes a branch instruction for an instruction which should be read to the microprocessor, when the break request signal 607 is activated. This type of branch instruction is called a "break instruction".
Operation will be explained with reference to FIG. 2, which shows a timing chart of the operation of the conventional microcomputer development support system.
When a user utilizes the break function, before execution of a debugging, file user sets the breakpoint register 64 with an address at which an interruption is to be generated. The comparator 66 compares an address outputted onto the address bus 603 from the microprocessor 61, with a content of the breakpoint register 64. If they are concordant with each other, the break request signal 607 is activated as shown by "A" in FIG. 2. If the break request signal 607 becomes active, the instruction substituting circuit 63 substitutes the break instruction as shown by "B" in FIG. 2, for the instruction which the microprocessor should read at that time in the user space access.
If the break instruction is executed by the microprocessor 61, the operation is branched to a head of a front-end monitor program within the user memory 62. As mentioned above, the front-end monitor 63 is in a space which is reserved in the user memory 62 and which is utilized by the microcomputer development support system. In accordance with the front-end monitor program, the cache memory within the microprocessor 61 is brought into a "cache off" condition, and the primary factor of the break is analyzed, as shown by "C" in FIG. 2.
The change into the "cache off" condition can be set in a program, and is actually realized in various manners by the microprocessor. For example, Intel's microprocessor "80486" and Motorola's microprocessors "68030" and "68040" are such that the status is changed by setting the status setting registers. Mips' R3000 adopts a method of setting a space to be executed in a "cache on" condition and a space to be executed in a "cache off" condition, on the basis of additional information for the memory space (the range designated by the address). Accordingly, the change into the "cache off" condition can be performed in either of the above mentioned methods with no problem. The switching of the address space is more preferable, since a high speed switching is possible, and therefore, it is suitable to realize a high speed operation.
If, as the result of the primary factor analysis, it is concluded that a trap is to be certainly performed, the memory space switching circuit 67 is instructed to control to the effect that, in succeeding accesses, the user memory 62 is not accessed, but the background monitor 65 is accessed. In the background monitor 65, a dump processing of an internal register is performed, and finally, a RETI (return-from-interrupt) instruction is executed so that the microprocessor 6I executes an original instruction before it was substituted by the break instruction (called a "resumption instruction"), as shown by "B", "C" and "D" in FIG. 2. Only the resumption instruction is executed under the "cache off" condition, but, after the resumption instruction has been executed, the cache is returned back to the "cache on" condition. These controls of the cache memory are performed on the basis of the front-end monitor.
The prior art microcomputer development support system as mentioned above needs to cause the front-end monitor to run on the user memory 62 to realize the break function in the microprocessor 61 including the cache memory therein. The following reasons are why the front-end monitor is necessary.
(1) There is no means other than the front-end monitor, for switching the operation to the background monitor 65. PA1 (2) The front-end monitor is required since the switching-over to the "cache off" condition is controlled in accordance with a monitor program. PA1 (3) There is no means for erasing the break instruction registered in the cache memory. Because of this, the resumption instruction after the break processing is executed under the "cache off" condition, so that the break instruction already registered in the cache memory is intentionally neglected. However, in the case that the same address as the address where the breakpoint is previously set, is accessed again, if the cache memory is hit, the break processing is repeated many times. As a result, the break point cannot be canceled until the end of the program. Therefore, it is necessary in the prior art for the front-end monitor to judge the necessity of break. PA1 instruction substituting means for tracing a memory access of the microcomputer and responding to a break request signal to supply to the execution unit of the microcomputer the predetermined branch instruction in place of an instruction which has been read from a predetermined address of a user memory to be supplied to the microcomputer; PA1 a background monitor configured to give the microprocessor a memory space which is separated from a user space but is peculiar to the microcomputer development support system, PA1 a breakpoint register for registering an address where a break processing is to be performed; PA1 a comparator comparing a content of the breakpoint register with an address outputted from the microcomputer, for generating the break request signal when coincidence is detected; PA1 a memory space switching circuit receiving the break acknowledge signal and the address outputted from the microprocessor, for separating the background monitor from the user memory, so that the background monitor functions as the memory space which is separated from the user space but is peculiar to the microcomputer development support system, whereby after the break request signal is activated, a processing is performed on the basis of a program of the background monitor, PA1 the microcomputer being configured to respond to the break request signal to put the cache memory into the "cache off" condition when it starts to execute the program of the background monitor, the microcomputer returning the cache memory into a "cache on" condition when the execution of the program of the background monitor is terminated.
In the case that the switching-over to the "cache off" condition can be controlled in accordance with the monitor program by the background monitor 602, since the foreground monitor (front-end monitor) and the background monitor are not distinguished from each other internally of the microprocessor 61, if this processing is performed by the background monitor, there is a possibility that an instruction registered in the cache memory is hit during an execution in the user space. Namely, a malfunction occurs. On the other hand, if the processing in question is carried out by the foreground monitor, since it is in the user memory space, even if the cache memory is hit, no malfunction occurs.
Because of the above mentioned reasons, in the prior art microcomputer development support system, the front-end monitor has been used for realizing the break function in the microprocessor internally containing the cache memory. However, the front-end monitor uses the resources of the user system (for an example, control signals for address bus of the user system, the user memory, etc.). This is disadvantageous in that a user's memory space (for examples, addresses and contents of programs) is inevitably limited.
Further, in a case that the microcomputer development support system itself utilizes the user system to debug a system under development, when malfunction occurs in the user system, the monitor program itself does not properly function. The inherent function of the microcomputer development support system itself cannot be exerted.
Furthermore, since, as mentioned in the above Item (3), the prior art microcomputer development support system does not have the means for erasing the break instruction remaining in the cache memory, it happens that the front-end monitor 603 operates unnecessarily even if the break processing was unnecessary. As a result, the real time operation is lost in the user program execution.